1. Field of the Invention
The present invention relates to the field of digital adders and more specifically to a three-to-two full adder cell.
2. Prior Art
Fundamental to the operation of virtually all digital microprocessors is the function of digital (i.e., binary) addition. Addition is used not only to provide numerical sums that the user is conscious of, but also in the implementation of numerous logic functions. In a typical microprocessor, many adders are used for these functions. When two digital words are added, it is common for one word to lag behind the other. A problem with this, particularly for circuits repeating the addition process several times is that substantial time is required to wait for the lagging input before the addition is performed. Since adders are often performing logic functions in critical paths, this waiting can slow up the microprocessor.
The present invention is an improved three-to-two adder in that fewer delays are encountered along critical paths in the adder. The adder therefore provides substantial improvement in terms of operation when compared to prior art adders. The present invention also reduces the number of transistors needed to implement the adder cell. This becomes significant when many of the adder cells are implemented together.
Prior art adders are shown in U.S. Pat. Nos. 4,783,757; 4,737,926; 4,905,180; and 4,901,270.